1. Field of the Invention
The present invention relates to a level converting circuit for converting the level of an input signal into a different level.
2. Description of the Background Art
To drive a display element, for example, a display panel composed of liquid crystal, a high voltage is applied to the display element, and desired display is achieved. In the case where the display panel is an active matrix type display panel, for example, a gate driver and a source driver are provided in order to drive the display panel. If each driver is constituted to have a high breakdown voltage, each transistor in the circuit should have, for example, a double diffusion structure, and as a consequence the constitution of the drive circuit becomes large. To prevent the constitutions of drivers from being enlarged, at the stage of processing signals, the processing of signals is conducted using a relatively low voltage, and the voltage value is changed just before applying the voltage to the display element to drive.
FIG. 34 is a block diagram showing a constitution of a conventional gate driver 11, FIG. 35 is a circuit diagram of a level shifter 13 contained in the gate driver 11, and FIG. 36 is a diagram showing a relation between input and output of the gate driver 11.
As shown in FIG. 34, the gate driver 11 is composed of a shift register 12, a level shifter 13, and an output buffer 14. The gate driver 11 is connected to, for example, n electrodes.
Plural voltages are supplied to the gate driver 11 from a power source circuit (not shown). Since the gate driver 11 is a gate driver for outputting a positive voltage on the basis of a negative voltage or a ground voltage Vss as a reference voltage, voltages VDD and VSS are supplied to the output buffer 14, each composition element is supplied in common with the reference voltage VSS of a negative power source side. The level shifter 13 is supplied with voltages VDD and VSS, and the shift register with voltages VSS and VCC. For example, voltage VDD is 30 V, voltage VCC is 5 V, and voltage VSS is 0 V, namely the ground voltage.
In the shift register 12 are inputted a clock signal CK and a start pulse SP whose signal level is shown in FIG. 36, and every time the clock signal CK is inputted, a signal S1 as shown in FIG. 36 is outputted to the level shifter 13. The high voltages of the clock signal CK and the start pulse SP are set to voltage VCC, and the low voltages thereof to voltage VSS, that is 0 V. The level shifter 13 is a circuit for shifting the level of an input signal and outputting the signal of the shifted level. As a structural example of the level shifter 13, FIG. 35 shows a level converting circuit which is disclosed in Japanese Unexamined Patent Publication JP-A 62-69719 (1987). In the following description, the level converting circuit is described as the level shifter 13.
The level shifter 13 is a circuit which converts an input signal S1 which varies between the voltages VCC and VSS to a signal S2 having an amplitude between the voltages VDD and VSS. The level shifter 13 includes an inverter circuit 16, P-channel MOS (metal oxide semiconductor) transistors Q1, Q2, and N-channel MOS transistors Q3, Q4. The inverter circuit 16 is composed of a P-channel MOS transistor Q5 and an N-channel MOS transistor Q6. In the inverter circuit 16, voltage VSS is supplied to a source of the transistor Q6, and voltage VCC is supplied to a source of the transistor Q5.
A signal fed to the level shifter 13 is supplied to gates of the P-channel MOS transistor Q5 and N-channel MOS transistor Q6 of the inverter circuit 16, and a gate of the N-channel MOS transistor Q4.
The output of the inverter circuit 16, namely the drain voltage of the transistors Q5, Q6 is supplied to a gate of the N-channel MOS transistor Q3 whose threshold is set to about 1 V. A drain of the N-channel MOS transistor Q3 is connected to a drain and a gate of the P-channel MOS transistor Q1, and to a gate of the P-channel MOS transistor Q2.
The sources of the P-channel MOS transistors Q1, Q2 are supplied with voltage VDD predetermined to be a higher level voltage than voltage VCC supplied to the input stage. Voltage VSS is supplied to the sources of the N-channel MOS transistors Q3, Q4. The voltage of an connection point between drains of the N-channel MOS transistor Q4 and the P-channel MOS transistor Q2 is supplied to the output buffer 14 as an output of the level shifter 13. The output of the level shifter 13 is shown as a signal S2 in FIG. 36.
To the level shifter 13 is inputted a signal changing between voltage VCC and voltage VSS, namely a signal having an amplitude of 5 V from the shift register 12. When the level of this signal changes from 5 V to 0 V, the N-channel MOS transistor Q6 is cut off, and the P-channel MOS transistor Q5 is made to conduct. Consequently, from the inverter circuit 16 is outputted voltage VCC, namely 5 V, and the N-channel MOS transistor Q3 determined at a threshold of 1 V is put into conduction state, and the gate potentials of the P-channel MOS transistors Q1, Q2 are lowered and the P-channel MOS transistors Q1, Q2 are set in conduction state. On the other hand, since the input has changed from 5 V to 0 V, the N-channel MOS transistor Q4 whose threshold is set to 1 V is cut off to be high in resistance. Therefore, voltage VDD is outputted from the shift register 13.
Likewise, when the level of the input signal changes from 0 V to 5 V, the P-channel MOS transistor Q5 is put in cutoff state, and the N-channel MOS transistor Q6 is set in conduction state. From the inverter circuit 16 is outputted voltage VSS, namely 0 V, and the N-channel MOS transistor Q3 is cut off and becomes a resistance of a high resistance value. When the N-channel MOS transistor Q3 is cut off, the P-channel MOS transistor Q1, Q2 are also cut off and become a resistance of a high resistance value. When the level of the signal fed into the level shifter 13 is 5 V, the N-channel MOS transistor Q4 is made to conduct. Consequently, from the level shifter 13 is outputted voltage VSS.
The output buffer 14 outputs the output of the level shifter 13 for a predetermined period to each electrode. The output of the output buffer 14 is shown as a signal S3 in FIG. 36.
In the gate driver 11 shown in FIG. 34, since the voltage VSS at the negative power source side is used as the reference voltage so that the positive voltage signal S2 is outputted (positive pour source specification), the level shifter 13 in FIG. 35 could be used, but when the voltage VDD at the positive power source side is used as the reference voltage and the negative voltage signal S7 is outputted (negative power source specification),the level shifter 13 cannot be used.
FIG. 37 shows the constitution of a gate driver 11a of the negative power source specification to which voltage VDD at the positive power source side is supplied in common, FIG. 38 shows a level shifter 17 in the gate driver 11a, and FIG. 39 shows a relation between input and output of the gate driver 11a.
In the gate driver 11a, the level shifter 13 in the gate driver 11 is replaced by a level shifter 17. As for other constituent elements, the gate driver 11a is different from the gate driver 11 only in input voltage, and the components are identified with the suffix "a" and the structural explanation is omitted.
The gate driver 11a is a driver for outputting a negative voltage whose reference voltage is a positive voltage VDD, and hence voltages VDD and VSS are supplied to the output buffer 14a, voltage VDD and voltage VSS are supplied to the level shifter 17, and voltage VDD and voltage VCC are supplied to the shift register 12a. For example, voltage VDD is set to 5 V, voltage VSS to -25 V, and voltage VCC to 0 V.
The level shifter 17 is a circuit which converts an input signal S6 which varies between the voltages VDD and VCC to a signal S7 having an amplitude between the voltages VDD and VSS. The level shifter 17 comprises an inverter circuit 16, P-channel MOS transistors Q11, Q12, and N-channel MOS transistors Q13, Q14. In the level shifter 17, the MOS transistors Q1 to Q4 in the level shifter 13 are respectively replaced by MOS transistors Q11 to Q14 of which conduction types are different from each other, and since the levels of the voltages fed to the respective MOS transistors are different, the output voltages are different. In the inverter circuit 16, voltage VCC is supplied to the source of the transistor Q6, and voltage VDD is supplied to the source of the transistor Q5. Moreover, voltage VDD is supplied to the sources of the P-channel MOS transistors Q11, Q12, and voltage VSS is supplied to the sources of the N-channel MOS transistors Q13, Q14.
A start pulse SP shown in FIG. 39, which is supplied to the shift register 12a has a high voltage of 5 V and a low voltage of 0 V. To the shift register 12a are supplied voltage VDD of 5 V and voltage VCC of 0 V, and when the start pulse SP is inputted, a signal S6 as shown in FIG. 39 is outputted on the basis of the signal level of the start pulse SP. The level shifter 17 outputs a signal S7 shown in FIG. 39 on the basis of an output from the shift register 12a. The output buffer 14a outputs a signal S8 shown in FIG. 39 to each electrode on the basis of the signal level of the signal S7 in a predetermined timing.
Herein, if the power source of the display device which supplies a voltage to the gate driver 11, as shown in FIG. 34, is so constituted that the voltage VSS of a predetermined level of the negative power source side is used as a reference voltage to output a positive voltage (positive power source specification), the level shifter 13 as shown in FIG. 35 may be directly used without modifying, but if the display device, as shown in FIG. 37, is so constituted that the voltage VDD of a predetermined level of the positive power source side is used as a reference voltage to output a negative voltage (negative power source specification), the level shifter 17 inverted in polarity as shown in FIG. 38 is required.
Since the prior art gate drivers 11, 11a are provided with either one of the level shifters 13, 17 which operate by either one of the reference voltages VSS and VDD of the gate drivers 11, 11a, it is necessary to select one from the gate driver 11 or 11a depending on whether the source of the display device outputs a positive voltage or a negative. Since the gate driver 11 or 11a is manufactured selectively according to the constitution of the output of the display device, manufacturing cost reduction by mass production can not be realized. Furthermore, if the gate drivers are provided with the level shifters 13 and 17 in common so as to change over one of the gate drivers to the other of the gate drivers in accordance with the constitution of the source, the gate driver can be used whether a positive voltage or a negative voltage is outputted, however, the constitution of the gate driver is enlarged.